feat: use riscv atomic immediate instructions for interrupt enable/disable

[kibels]

The existing Csr.write(), Csr.set() and Csr.clear() functions only allow the "r" register constraint, so always generate as two instructions e.g.

li a0, 8
csrs mstatus, a0

By refining the implementation a bit to detect when the value is comptime known and small enough to fit in the u5 immediate, this change allows the compiler to generate single atomic instructions for small immediates, like when setting the global interrupt enable bits.

csrsi mstatus, 8

The interface is changed slightly, to accept the packed struct T directly for set/clear instead of an anonymous struct. This has some benefits like a known result type, and allows detection of whether the passed in value is comptime known which the get_bits() necessary for .modify() to work obscures.

A before/after of the codegen can be observed in: https://godbolt.org/z/sKeboeoWv

CSRs that are meant to be used with these interfaces should have default field values of 0, so that the set/clear mask can be generated without providing all of the fields.

[github-actions]

🔍 Lint Results

Found 2 issues on changed lines in 1 file:

• modules/riscv32-common/src/riscv32_common.zig: 2 issues

Updating with new lint results

[github-actions]

🔍 Lint Results

[Grazfather]

Can you rebase/merge in main? #864 might need an update since you added a type to mpp

EDIT: Not needed